New chip design framework aims to improve performance by reducing signal delay as traditional transistor scaling slows
Huawei Technologies has unveiled a new chip design approach called the “Tau Scaling Law,” positioning it as a potential breakthrough for the future of semiconductor development as traditional transistor miniaturisation approaches physical and economic limits.
The announcement was made at the 2026 IEEE International Symposium on Circuits and Systems in Shanghai, where Huawei semiconductor executive He Tingbo described the concept as “a new guiding principle for the future of semiconductors.”
The proposed framework is presented as an alternative to Moore’s Law, the long-standing industry benchmark which suggests that transistor density doubles roughly every 18 to 24 months. That principle has slowed in recent years as further shrinking of transistor sizes becomes increasingly difficult and costly.
According to Huawei, the Tau Scaling Law shifts the focus away from reducing transistor size and instead targets reduction in overall processing time across computing systems.
Named after the Greek letter tau (τ), commonly used in physics to represent time constants, the framework aims to minimise signal delay across electronic systems to enhance performance and energy efficiency.
“The core objective is to optimise task completion time rather than only shrinking individual transistors,” He Tingbo said during the keynote address.
Huawei said the approach enables chips to become faster, more energy-efficient and more densely integrated without relying solely on traditional geometric scaling.
A key component of the strategy is a technology called “LogicFolding,” which reorganises circuit layouts to shorten the physical distance that electrical signals travel within chips.
The company said reduced signal paths help lower resistance and capacitance, improving processing speed while increasing effective transistor density.
He Tingbo said Huawei has already applied the Tau Scaling Law across multiple layers of chip design and system development. Over the past six years, the company claims to have designed and mass-produced 381 chips based on the new model for various industry applications.
Huawei also announced plans to release new Kirin processors later in 2026 that will fully integrate the LogicFolding architecture, which it says will deliver significant performance improvements.
Looking ahead, the company projected that by 2031, high-end chips developed under the Tau Scaling framework could achieve transistor densities comparable to advanced 1.4-nanometer manufacturing processes.
Huawei further called for increased global collaboration in semiconductor research and development.
“We believe openness and collaboration are key to driving ongoing progress in the semiconductor industry,” He Tingbo said, inviting researchers, engineers and industry partners worldwide to participate in future development efforts.
